The present invention relates to the fabrication of integrated circuits. More particularly, the present invention relates to improved techniques for reducing capacitive coupling between conductive lines and/or conductive plugs in an integrated circuit (IC).
In a typical integrated circuit, conductive lines, e.g., metal lines, may be employed to couple selected devices on a substrate together to achieve the designed functionality. In modern, vertically integrated IC's, multiple conductive layers may be employed to satisfy the interconnect requirement while minimizing the size of the IC. These conductive layers are typically insulated from one another by one or more dielectric layers. Vias may then be employed, where desired, to interconnect conductive lines in different conductive layers together.
To facilitate discussion, FIGS. 1-6 depict the conventional process for forming the upper level conductive lines in multiple conductive layers on an integrated circuit. The structures formed by the figures herein may be employed, for example, in fabricating dynamic random access memory (DRAM) circuits. Although only the upper level conductive lines and the latter stages of forming multi-level conductive lines are shown to simplify illustration, it should be borne in mind that the invention disclosed herein applies equally well to other conductive layers that may underlie the upper level conductive lines. Referring initially to FIG. 1, conductive lines 103, 105, 114, and 106, which are formed from conductive layer 108 (such as a metal layer), are shown disposed on a substrate 110. Substrate 110 may represent, for example, a silicon substrate and may include a plurality of devices implemented therein. Conductive lines 103, 105, 114, and 106 may represent, for example, aluminum interconnect lines and may be etched out of conductive layer 108 using a conventional etch process.
Above conductive layer 108, there is deposited a first dielectric layer 112. After being deposited, first dielectric layer 112 is typically planarized by a conventional planarizing process such as chemical-mechanical polish (CMP). In FIG. 2, a dielectric etch step is then employed to etch a via 203 and a via 205 through first dielectric layer 112 using a photoresist mask 204. Although vias 203 and 205 are shown to have tapered walls, the via walls may in fact be vertical if desired.
In FIG. 3, a conductive layer 302 comprising, for example, aluminum or one of its alloys, is deposited above first dielectric layer 112 and into vias 203 and 205. Inside vias 203 and 205, the conductive material forms conductive plugs 303 and 305 respectively. These conductive plugs 303 and 305 serve to interconnect conductive layer 302 with respective conductive lines 103 and 105 in underlying conductive layer 108.
Alternatively, a layer of plug material may be deposited above first dielectric layer 112 of FIG. 2 and etched or polished back to form conductive plugs within vias 203 and 205. For example, the conductive plugs may be formed of tungsten. Thereafter, another conductive layer, e.g., aluminum or one of its alloys, may be blanket deposited above dielectric layer 112 to form electrical contact with the conductive plugs formed earlier.
In FIG. 4, conductive layer 302 is etched using an appropriate photoresist mask 502 to form conductive lines 503, 505, and 508 as shown. Conductive line 503 is shown coupled to conductive line 103 through conductive plug 303 in via 203 while conductive line 505 is shown coupled to conductive line 105 through conductive plug 305 in via 205.
In FIG. 5, a liner layer 502, typically representing a thin (e.g., about 1,000 angstroms thick) TEOS layer is blanket deposited over conductive lines 503, 505, and 508 as well as above the surface of dielectric layer 112 (after the photoresist that was employed to etch the conductive lines has been removed). Thereafter, a nitride passivation layer 602 is deposited above liner layer 502 (FIG. 6). Nitride layer 602 may be, for example, about 7,000 angstroms thick. As shown in FIG. 6, nitride layer 602 also fills in the trench between conductive lines 503, 505, and 508.
It has been found that the prior art multi-level conductive structure of FIG. 6 has certain disadvantages. For example, a high level of capacitive coupling has been found to exist among the various conductive lines and conductive plugs of the prior art multi-level conductive structure. With reference to FIG. 6, for example, capacitive coupling exists between adjacent conductive lines 503 and 505 through nitride layer 602 and first dielectric layer 112. The level of capacitive coupling therebetween has been found to be relatively high due to the high dielectric constant of the nitride material (e.g., a dielectric constant of about 7-9 for a typical nitride layer) and the high dielectric constant of the underlying oxide dielectric (e.g., a dielectric constant of about 4 for a typical oxide layer).
Further, capacitive coupling exists between conductive line 503 and underlying conductive line 103, as well as between conductive line 505 and underlying conductive line 105. Since some of the field lines traverse the relatively high capacitance dielectric layer 112, the level of capacitive coupling therebetween has been found to be relatively high as well.
Further, capacitive coupling has also been found among adjacent conductive plugs, e.g., between conductive plug 303 and 305 through dielectric layer 112 of FIG. 6. Again, due to the relatively high capacitance of dielectric layer 112, the capacitive coupling between adjacent conductive plugs has been found to be relatively high as well.
As can be appreciated by those skilled in the art, the high level of capacitive coupling among the conductive lines and plugs of the prior art multilevel conductive structure increases the time delays as well as contributes to a high level of cross-talk and capacitive loss in the final integrated circuit, thereby degrading performance. Further, the high level of capacitive coupling requires a higher operating voltage, which increases heat dissipation and delay during operation. This is particularly true for capacitive coupling to and from conductive lines in the uppermost metal layer since these conductive lines typically contain the largest and longest metal leads (e.g., up to 1 micron high by 0.8 micron wide and up to several millimeters long), since they are designed carry power and ground to the rest of the IC. A high level of capacitive coupling to and from these upper level metal leads tends to greatly degrades the IC's performance in terms of capacitance, delay, and power dissipation.
In view of the foregoing, there are desired improved multi-level conductive structures, and methods therefor, that advantageously reduce the capacitive coupling among their various conductive lines and plugs in order to improve performance.